1. Field of the Invention
The present invention generally relates to a driving apparatus for a recording medium by which the moving speed of a recording medium relative to a pickup is kept constant. More particularly, this invention relates to a driving apparatus for a recording medium which is suitable for use with, for example, an optical compact disc player.
2. Description of the Prior Art
In the optical compact disc, by way of example, a signal is generally recorded on the disc as a spiral track from the inner periphery of the disc to its outer periphery at the constant linear velocity. Therefore, when such optical compact disc is reproduced, a servo has to be applied for the disc rotation so that the disc is rotated at the same constant linear velocity as that upon recording.
In that case, it has been proposed that a distance between the reproducing position of, for example, a pickup and the center of the disc is detected, the rotation speed of the disc is measured by calculating the detected distance and thereby the servo is applied to the disc rotation on the basis of the measured rotation speed. This previously proposed method, however, urges the calculating circuit and so on to be complicated, and also the servo accuracy is not so high.
By the way, in the recording of the compact disc, the coding according to the so-called run length limited code system is generally employed in which the minimum and maximum numbers of a series of, for example, "0"s are determined, and in which such a pattern in which "0" continues at maximum (for example, 11) exists without failure at every predetermined period as a frame synchronizing signal.
Accordingly, the present inventor has previously proposed the servo circuit as shown in FIG. 1. As shown in FIG. 1, a signal reproduced from a disc (not shown) by a photodetector 1 is suppled to a waveform converting circuit 2 and then to a differentiating circuit 3 from which is reproduced the signal which corresponds to "0" or "1". This reproduced signal is supplied to a first fixed contact A of a selector circuit 4. The signal from the differentiating circuit 3 is also supplied to a synchronizing separating circuit 5. The synchronizing separating circuit 5 includes a PLL (phase locked loop) in which a frame synchronizing signal is separated in synchronism with the clock signal in the reproduced signal, while the lock range of the PLL is made narrow and the indicating signal of "0" is delivered when the PLL is not locked. The frame synchronizing signal thus separated is supplied to a second fixed contact B of the selector circuit 4. Further, there is provided a reference clock generator 6. This reference clock generator 6 generates a reference clock signal with the frequency same as the clock signal (for example, 2.16 MHz) in the reproduced signal when the predetermined servo is made effective. This reference clock signal is supplied to a frequency dividing circuit 7 which produces a signal corresponding to four frame synchronizing signals (four frames). This signal is supplied to a third fixed contact C of the selector circuit 4.
The indicating signal indicative of the locked state of the PLL from the synchronizing separating circuit 5 is supplied to the selector circuit 4 as its control signal so that a movable contact D of the selector circuit 4 is connected to the fixed contact A during the period through which this indicating signal is "0". Usually, the movable contact D of the selector circuit 4 is connected to its fixed contact B. The signal from the selector circuit 4 is supplied to a reset terminal of a counter 8, while the clock signal from the clock generator 6 is supplied to the count terminal of the counter 8.
When the continuous number of "0" in the frame sychronizing signal is for example, 11, the output regarding the count value [8] from the counter 8 is supplied to a NAND circuit 9. Also, the output regarding the count value [2] from the counter 8 is supplied to the NAND circuit 9 through a delay circuit 10. Thus, the NAND circuit 9 normally generates an output "1", and at a time point corresponding to a time point when the counter valve becomes [11] after a predetermined delay time since the count value has become [10], the output of the NAND circuit 9 becomes "0". The output signal from the NAND circuit 9 is supplied to the enable terminal of the counter 8 so that the output of the counter 8 is fixed to the count value [11]. The output from the NAND circuit 9 is also supplied to the selector circuit 4 as its control signal so that in the period during which this signal is " 0" the movable contact D of the selector circuit 4 is connected to the fixed contact C.
Further, the output from the NAND circuit 9 is supplied through an inverter 11, a low-pass filter 12 and a resistor 13 to an inverter 14.
The clock signal from the clock generator 6 is supplied to a frequency dividing circuit 15 which then generates a reference frame synchronizing signal. This reference frame synchronizing signal and the reproduced frame synchronizing signal from the synchronizing separating circuit 5 are fed to a flip-flop circuit 16 which then generates an output corresponding to the phase difference therebetween. This output is supplied through a NAND circuit 17, a low-pass filter 18 and a resistor 19 to the inverter 14.
Thus from the inverter 14 is derived the output corresponding to the period in which the output from the counter 8 is [11] and corresponding to the phase difference between the reference frame synchronizing signal and the reproduced frame synchronizing signal.
The output from the inverter 14 is supplied to a NAND circuit 20 and the lock indicating output from the synchronizing separating circuit 5 is supplied to the NAND circuit 20. The output from the NAND circuit 20 is supplied to the bases of an npn transistor 21 and a pnp transistor 22, while the output from the inverter 14 is supplied to the bases of an npn transistor 23 and an pnp transistor 24. The collectors of the transistors 21 and 23 are connected together to a voltage source terminal V.sub.cc, while the collectors of the transistors 22 and 24 are together grounded. Further, the emitters of the transistors 21 and 22 are connected together, while the emitters of the transistors 23 and 24 are connected together. A spindle motor 25 for rotating a disc is connected between the above emitter connection points.
With this circuitry, until the PLL in the synchronizing separating circuit 5 is locked, the signal "0" is supplied to the NAND circuit 20 and hence the output from the NAND circuit 20 is "1" so that the transistor 21 is turned on but the transistor 22 is turned off. At that time, since the movable contact D of the selector circuit 4 is connected to the fixed contact A, the reproduced signal is directly supplied to the counter 8. As a result, when the disc rotation is slow and the signal is dull, the count value of the counter 8 quickly becomes [11] so that the output from the NAND circuit 9 becomes "0". By this output, the counter 8 is stopped and the selector circuit 4 is changed in position or its movable contact D is connected to the fixed contact C so that the counter 8 is stopped for four frame periods. Since the output from the NAND circuit 9 is "0", the output from the inverter 14 becomes "0". Thus, the transistor 23 is turned off and the transistor 24 is turned on to thereby allow a current to flow through the spindle motor 25 in the arrow direction, thus increasing the rotation speed of the spindle motor 25.
In consequence, the rotation speed of the disc is being continuously increased until the maximum interval of the signals becomes approximately 11 clocks.
At that time, the PLL in the synchronizing separating circuit 5 is locked, the selector circuit 4 is changed in position or its movable contact D is connected to the fixed contact B and the signal "1" is supplied to the NAND circuit 20. As a result, the separated frame synchronizing signal is supplied to the counter 8. When the length of the synchronizing signal reaches more than 11 clocks, the output of the NAND circuit 9 becomes "0"during four frame periods, the output from the inverter 14 becomes "0", the output from the NAND circuit 20 becomes "1" so that the transistors 21 and 24 are turned on and the transistors 22 and 23 are turned off to thereby allow the current to flow through the spindle motor 25 in the arrow direction. Therefore, the rotation speed thereof becomes high. On the other hand, when the length of the synchronizing signal becomes less than 11 clocks, the output from the NAND circuit 9 becomes "1", the output from the inverter 14 becomes "1" and the output from the NAND circuit 20 becomes "0" so that the transistors 21 and 24 are turned off and the transistors 22 and 23 are turned on to thereby allow the current to flow through the spindle motor 25 in the direction counter to the arrow direction, thus lowering the rotation speed thereof.
As a result, the rotation speed servo is applied to the disc so as to make the length of the synchronizing signal equal to 11 clocks.
At that time, the flip-flop circuit 16 produces the output signal which becomes "1" during the period from the reproduced synchronizing signal to the reference synchronizing signal and "0" during the period from the reference synchronizing signal to the succeeding reproduced synchronizing signal. For this reason, when the reproduced synchronizing signal gets behind the position at which the phase difference between the reproduced synchronizing signal and the reference synchronizing signal is 180.degree., the period during which the signal is "0" becomes long, while when the reproduced synchronizing signal goes ahead of that position, the period during which the signal is "1" becomes long. And, when the signal is "0", the output from the NAND circuit 17 becomes "1", the output from the inverter 14 becomes "0" and the output from the NAND circuit 20 becomes "1", thus the rotation speed of the spindle motor 25 is raised. Conversely, when the signal is "1", the rotation speed of the spindle motor 25 is lowered.
As a result, the rotation phase servo is applied to the disc so as to make the synchronizing signal at the predetermined position.
As described above, the rotation speed servo of the constant linear velocity and the rotation phase servo are applied to the disc. In this case, since the pull-in of the rotation speed of the disc at the beginning is carried out also by the use of the counter 8, the pull-in operation of the speed can be made by a simple circuitry.
In the case of such previously proposed servo circuit, however, since the rotation speed servo is performed by detecting the length (11 clocks) of the synchronizing signal with the clock signal, the accuracy of the rotation speed servo becomes as significantly rough as 1/11.
If in the phase servo system, by way of example, the frame synchronizing signal is multiplied and the phase servo is made effective with the frequency (for example, 7.35 kHz) higher than that of the inherent frame synchronizing signal, the accuracy of the speed servo has to be raised. In that case, the above rough servo can not raise the frequency of the phase servo and hence the superior servo can not be carried out.